An Efficient Hybrid Parallel Prefix Adders for Reverse Converters using QCA Technology
نویسندگان
چکیده
In many building blocks of microprocessors and digital signal processing chips, adders are frequently available in their critical paths. Adders can also be used for subtraction, multiplication and division. One of the important basic arithmetic operations is addition. There are several structures like Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) to perform the addition. Parallel prefix adders speed up the addition operation when compared to the other structures. Generally these adders provide less power consumption, but these consume more power when these are used in reverse converters. To reduce this high power consumption, hybrid parallel prefix adders can be used. In this paper, two structures namely, Hybrid Regular Parallel Prefix XOR/OR (HRPX) Adder and Hybrid Modular Parallel Prefix Excess-one (HMPE) Adder are discussed which uses modulo addition. Further these two adders are implemented using the Quantum dot cellular automata (QCA) technology, which reduces the delay. This entire work is done in Xilinx 13.2 tool ISE simulator.
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